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d a t a sh eet objective speci?cation file under integrated circuits, ic01 august 1994 integrated circuits philips semiconductors TDA1549T stereo 4f s data input up-sampling filter with bitstream continuous calibration dac (bcc-dac1)
august 1994 2 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T features easy application finite-duration impulse-response (fir) filtering and noise shaping incorporated 2nd-order noise shaper wide dynamic range (true 18-bit resolution) low total harmonic distortion no zero-crossing distortion superior signal-to-noise ratio bitstream continuous calibration conversion concept inherently monotonic voltage output (1.5 v rms) at line drive level single supply rail (3.8 to 5.5 v) optimum output voltage level over the entire supply range small outline packaging (so16) wide operating temperature range ( - 30 to +85 c) standard japanese input format no analog post-filtering required low power consumption integrated operational amplifiers. general description the TDA1549T (bcc-dac1) is the first of a new generation of digital-to-analog converters featuring a unique combination of bitstream and continuous calibration concepts. a system of digital filtering, high oversampling, 2nd order noise shaping and continuous calibration digital-to-analog conversion ensures that only simple 1st order analog filtering is required. the circuit accepts 18-bit four times oversampled input data (4f s ) in standard japanese format. internal fir filters remove the main spectral components and increase the sampling rate to 96 times (96f s ). a 2nd order noise shaper converts this oversampled data to a 5-bit data stream. for low signal levels the converter operates in the 1-bit bitstream mode with attendant high differential linearity. higher level signals are reproduced using the dynamic continuous calibration technique, thereby guaranteeing high linearity independent of process variations, temperature effects and product ageing. high-precision, low-noise amplifiers convert the digital-to-analog current to an output voltage capable of driving a line output. externally connected capacitors perform the required 1st order filtering so that no further post-filtering is required. internal reference circuitry ensures that the output voltage is proportional to the supply voltage, thereby making optimum use of the supply voltage over a wide range (3.8 to 5.5 v). this unique configuration of bitstream and continuous calibration techniques, together with a high degree of analog and digital integration, results in a digital-to-analog conversion system with true 18-bit dynamic range, high linearity and simple low-cost application. ordering information type number package name description version TDA1549T so16 plastic small outline package; 16 leads; body width 7.5 mm sot162 - 1
august 1994 3 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T quick reference data notes 1. all v dd and ground pins must be connected externally to the same supply. 2. measured with v ddd , v dda and v ddo = 5 v at input data code 00000h. 3. measured with v ddd , v dda and v ddo = 3.8 v at input data code 00000h. symbol parameter conditions min. typ. max. unit v ddd digital supply voltage note 1 3.8 5.0 5.5 v v dda analog supply voltage note 1 3.8 5.0 5.5 v v ddo operational ampli?er supply voltage note 1 3.8 5.0 5.5 v i ddd digital supply current note 2 - 12 18 ma i dda analog supply current note 2 - 5.5 8 ma i ddo operational ampli?er supply current note 2 - 6.5 9 ma p tot total power dissipation note 2 - 120 185 mw note 3 - 50 - mw v fs(rms) full-scale output voltage (rms value) v ddd =v dda = v ddo = 5 v 1.425 1.500 1.575 v (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db signal level -- 90 - 83 db - 0.003 0.007 % at - 60 db signal level -- 48 - 40 db - 0.40 1.0 % at - 60 db signal level; a-weighted -- 50 - db - 0.38 - % s/n signal-to-noise ratio at bipolar zero a-weighted; at code 00000h 100 110 - db t cs current setting time to 1 lsb - 0.1 -m s br input bit rate at data input -- 9.216 mbits f bck input clock frequency -- 9.216 mhz tc fs full-scale temperature coef?cient at analog outputs (vol and vor) - 100 x 10 - 6 - t amb operating ambient temperature - 30 - +85 c
august 1994 4 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T block diagram fig.1 block diagram.
august 1994 5 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T pinning symbol pin description ws 1 word select input bck 2 bit clock input test 3 test input; pin should be connected to ground vol 4 left channel output filtcl 5 capacitor for left channel 1st order ?lter function; should be connected between pins 4 and 5 filtcr 6 capacitor for right channel 1st order ?lter function; should be connected between pins 6 and 7 vor 7 right channel output v ref 8 internal reference voltage for output channels ( 1 2 v dd ) v sso 9 operational ampli?er ground v ddo 10 operational ampli?er supply voltage v dda 11 analog supply voltage v ssa 12 analog ground n.c. 13 not connected (this pin should be left open-circuit) v ssd 14 digital ground v ddd 15 digital supply voltage data 16 data input fig.2 pin configuration.
august 1994 6 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T functional description general the TDA1549T cmos digital-to-analog bitstream continuous calibration converter incorporates internal digital filtering which increases the oversampling rate of 4f s input data to 96f s , and removes the spectral data components around 4f s , 8f s , and 12f s . a 2nd order noise shaper operating at 96f s outputs a 5-bit data bitstream to the dacs. the filtering required for waveform smoothing and out-of-band noise reduction is achieved by simple 1st order analog post-filtering (see fig.3). the combination of noise shaping and bitstream continuous calibration digital-to-analog conversion enables high performance and extremely low noise to be achieved. input the circuit accepts four times oversampled data in 18-bit two's complement standard japanese format with msb first. left and right data channel words are time multiplexed. the input format is illustrated in fig.5. the bit clock (bck) operates at 192f s , i.e. 48 times the word select (ws) frequency of 4f s . oversampling ?lter the oversampling filter consists of: a 7th order half-band low-pass fir filter which increases the oversampling rate from 4 times to 8 times. this removes the spectral components around 4f s and 12f s (see fig.3). a linear interpolation section which increases the oversampling rate to 16 times. this removes the spectral components around 8f s . a sample-and-hold section which provides another 6 times oversampling to 96 times. the zero-order hold characteristic of this sample-and-hold section plus the 1st order analog filtering removes the spectral components around 16f s . passband ripple is within 0.1 db. stopband attenuation is >50 db around multiples of the sampling frequency. noise shaper the 2nd-order digital noise shaper converts the 18-bit data at 96f s into a 5-bit bitstream, while shifting in-band quantization noise to frequencies well above the audio band. for low signal levels the noise shaper output is a 1-bit bitstream. this noise shaping technique used in combination with a special data code and bitstream dac enables extremely high signal-to-noise ratios to be achieved. data encoder the data encoder converts the 5-bit two's complement output data from the noise shaper to a 32-bit thermometer code. in traditional unidirectional current converters, half of the full-scale current flows to the output during small signal reproduction. the thermal noise and substrate crosstalk components present in this current severely restrict the dynamic range which can be attained. in this bcc-dac1 true low-noise performance is achieved using a special data code and bidirectional current sources. the special data code guarantees that only small values of current flow to the output during small-signal passages while larger positive or negative signals are generated using the bidirectional current sources. for every change in the 18-bit input sample only one current source or current sink is switched on. this intrinsically monotonic thermometer code ensures the high differential linearity, zero crossover distortion and superior signal-to-noise ratio associated with bitstream conversion.
august 1994 7 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T continuous calibration dac the stereo 5-bit dac uses the dynamic continuous calibration technique. the dac currents (16 sources and 16 sinks) of each channel are repeatedly generated from one single reference current. this duplication is based on an internal charge storage principle and has an inherently high accuracy which is insensitive to ageing, temperature and process variations. figure 4 shows one such current calibration source. during calibration the cell is connected to the reference current sink i ref via switch s2. the calibration transistor m1 is connected as an mos diode via the switch s1 forcing its gate potential to assume a value so that the total current of the calibration cell is equal to the reference current. after calibration the gate of m1 is allowed to float. the gate capacitance c gs retains its potential and the current through the cell remains exactly equal to the reference current. this current is now connected to the output. each digital-to-analog current source and each current sink is calibrated precisely in this way. operational ampli?ers high precision, low-noise amplifiers together with the internal conversion resistors r conv1 and r conv2 convert the dac output current to a voltage capable of driving a line output. this voltage is available at vol and vor (1.5 v rms typical). connecting external capacitors c ext1 and c ext2 between filtcl and vol and filtcr and vor respectively, provides the required 1st-order post-filtering for the left and right channels (see fig.1). the combinations of r conv1 with c ext1 and r conv2 with c ext2 determine the 1st order fall-off frequencies. internal reference circuitry internal reference circuitry ensures that the output voltage signal is proportional to the supply voltage, thereby maintaining maximum dynamic range for supply voltages from 3.8 to 5.5 v and making the circuit also suitable for battery-powered applications. fig.3 filter and noise shaper characteristics.
august 1994 8 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T fig.4 calibration principle. (a) calibration. (b) operation.
august 1994 9 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model: c = 100 pf; r = 1500 w . 2. machine model: c = 200 pf; l = 0.5 m h; r = 10 w . thermal characteristics handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. quality specification quality specification in accordance with snw-fq-611 is applicable. symbol parameter conditions min. max. unit v ddd digital supply voltage - 7.0 v v dda analog supply voltage - 7.0 v v ddo operational ampli?er supply voltage - 7.0 v t xtal maximum crystal temperature - +150 c t stg storage temperature - 65 +150 c t amb operating ambient temperature - 30 +85 c v es electrostatic handling note 1 - 2000 +2000 v note 2 - 200 +200 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 110 k/w
august 1994 10 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T characteristics v ddd =v dda =v ddo =5v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v ddd digital supply voltage note 1 3.8 5.0 5.5 v v dda analog supply voltage note 1 3.8 5.0 5.5 v v ddo operational ampli?er supply voltage note 1 3.8 5.0 5.5 v i ddd digital supply current note 2 - 12 18 ma i dda analog supply current note 2 - 5.5 8 ma i ddo operational ampli?er supply current note 2 - 6.5 9 ma p tot total power dissipation note 2 - 120 185 mw note 3 - 50 - mw rr ripple rejection note 4 - 25 - db digital inputs; pins ws, bck and data v ih high level input voltage 0.7v dd - v dd + 0.5 v v il low level input voltage - 0.5 - 0.3v dd v |i lih | high level input leakage current v ih =v ddd =5v -- 10 m a |i lil | low level input leakage current v ih =v ssd =0v -- 10 m a c i input capacitance -- 10 pf timing (see fig.6) o perating frequency f bck bit clock frequency - 192f s - hz f ws word select frequency - f bck /48 - hz i nput frequency f bck clock frequency -- 9.216 mhz br bit rate data input -- 9.216 mhz f ws word select input frequency -- 192 khz t r rise time -- 32 ns t f fall time -- 32 ns t cy bit clock cycle time 108 -- ns t h bit clock high time 22 -- ns t l bit clock low time 22 -- ns t su data set-up time 32 -- ns t h data hold time 2 -- ns t hws word select hold time 2 -- ns t suws word select set-up time 32 -- ns filter characteristics (see fig.3) pbr pass-band ripple < 20 khz - 0.1 - db sba stop-band attenuation note 5 50 -- db
august 1994 11 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T notes 1. all v dd and v ss pins must be connected externally to the same supply. 2. measured with v ddd =v dda =v ddo = 5 v at input data code 00000h. 3. measured with v ddd =v dda =v ddo = 3.8 v at input data code 00000h. 4. v ripple = 1% of the supply voltage and f ripple = 100 hz. ripple rejection rr to v dda is dependent on the value of the external capacitor (c ext3 in fig.1) connected to v ref . the value quoted here assumes c ext3 =1 m f. 5. around multiples of 4f s . 6. measured with a 1 khz, 0 db, 18-bit sine wave generated at a sampling rate of 192 khz. (thd + n)/s measured over a bandwidth from 20 hz to 20 khz. 7. measured with a 1 khz, - 60 db, 18-bit sine wave generated at a sampling rate of 192 khz. (thd + n)/s measured over a bandwidth from 20 hz to 20 khz. 8. measured with a 1 khz, - 60 db, 18-bit sine wave generated at a sampling rate of 192 khz. (thd + n)/s measured over a bandwidth from 20 hz to 20 khz and filtered with a-weighted characteristic. 9. measured with a 0 db, 18-bit sine wave from 20 hz to 20 khz generated at a sampling rate of 192 khz. (thd + n)/s measured over a bandwidth from 20 hz to 20 khz. reference values v ref reference voltage level 2.45 2.5 2.55 v r conv current-to-voltage conversion resistance 1.6 2.2 2.8 k w analog outputs; pins vol and vor res resolution -- 18 bit v fs(rms) full-scale output voltage (rms value) 1.425 1.5 1.575 v v off output voltage dc offset with respect to reference voltage level v ref - 80 - 65 - 50 mv tc fs full-scale temperature coef?cient - 100x10 - 6 - (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db input level; note 6 -- 90 - 83 db - 0.003 0.007 % at - 60 db input level; note 7 -- 48 - 40 db - 0.40 1.0 % at - 60 db input level; a-weighted; note 8 -- 50 - db - 0.32 - % at 0 db input level; 20 hz to 20 khz; note 9 -- 90 - 83 db - 0.003 0.007 % s/n signal-to-noise ratio at bipolar zero a-weighted; at code 00000h 100 110 - db t cs current setting time to 1 lsb - 0.1 - ms a cs channel separation 85 100 - db | d v o | unbalance between outputs - 0.2 0.3 db |z o | dynamic output impedance - 10 - w r l output load resistance 3 -- k w c l output load capacitance -- 200 pf symbol parameter conditions min. typ. max. unit
august 1994 12 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T fig.5 format of input signals. fig.6 timing of input signals.
august 1994 13 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T application information a typical application diagram is illustrated in fig.7. the left and right channel outputs can drive a line output directly. fig.7 application diagram. (1) c = 100 nf (chip capacitor).
august 1994 14 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T in fig.8 measurements were taken with an 18-bit sine wave generated at a sample rate of 192 khz. the (thd + n)/s was measured over a bandwidth of 20 hz to 20 khz. the graph was constructed from average measurement values of a small amount of engineering samples. no guarantee for typical values is implied. fig.8 total harmonic distortion plus noise-to-signal ratio as a function of signal frequency. (1) level = - 60 db. (2) level = 0 db.
august 1994 15 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T in fig.9 measurements were taken with an 18-bit sine wave generated at a sample rate of 192 khz. the (thd + n)/s was measured over a bandwidth of 20 hz to 20 khz and filtered with a-weighted characteristic. the graph was constructed from average measurement values of a small amount of engineering samples. no guarantee for typical values is implied. fig.9 total harmonic distortion plus noise-to-signal ratio as a function of signal level; (a-weighted).
august 1994 16 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T package outline handbook, full pagewidth 7.6 7.4 10.65 10.00 a mbc233 - 1 0.3 0.1 2.45 2.25 1.1 0.5 0.32 0.23 1.1 1.0 0 to 8 o 2.65 2.35 detail a s 10.5 10.1 0.1 s 18 9 16 pin 1 index 0.9 0.4 (4x) 0.25 m (16x) 0.49 0.36 1.27 fig.10 plastic small outline package; 16 leads; body width 7.5 mm; (so16; sot162-1). dimensions in mm.
august 1994 17 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T soldering plastic small-outline packages b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
august 1994 18 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac (bcc-dac1) TDA1549T notes
august 1994 19 philips semiconductors objective speci?cation stereo 4f s data input up-sampling ?lter with bitstream continuous calibration dac TDA1549T notes
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(02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd34 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands

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